“Can We Eliminate Synthesis From A Programmer’s Development Path?”
Thursday, Nov. 16 @ 1:00 pm, Larsen 310
David Andrews, Mullins Endowed Chair of Computer Engineering, University of Arkansas
Abstract
Reconfigurable manycore chips are our semiconductor industries next solution to provide more energy efficient scalable architectures for data centers and warehouse scale computers. A recent report from the United States Bureau of Labor Statistics showed that only 83,000 computer hardware engineers are employed within the United States. This is compared with the 1.3 million software programmers. These statistics show that the number of hardware designers is insufficient to handle the potential scale of FPGAs deployed throughout future data centers and warehouse scale computers. Thus it has now become imperative that we develop a realistic pathway for programmers, not just hardware engineers, to compile custom high-performance circuits into the reconfigurable manycores that will populate our data centers and warehouse scale computers.
Current state of the art approaches to create circuits requires the complete accelerator functionality to be first defined within a vendors CAD tool, then synthesized. In this talk I will outline a new approach we are investigating that moves synthesis out of the programmer’s development path. Our approach includes the introduction of a platform independent interpreter language and a run time system that can just in time assemble hardware components within a new overlay. Experimental results will be presented showing how the approach allows compilation of accelerators on both single chip heterogeneous multiprocessor systems as well as a commercial reconfigurable cluster with 24 FPGAs.
Biography
David Andrews holds the Mullins Endowed Chair of Computer Engineering at the University of Arkansas. He worked as a research scientist at General Electric’s Electronics Laboratory and Advanced Technology Laboratories on parallel and distributed embedded real time systems, he has held faculty positions at the University of Arkansas and the University of Kansas, and he has led research sponsored by DARPA, NSF and industry on parallel real time architectures, run time systems and middleware for hybrid CPU/FPGA MPSoCs. He earned his PhD in Computer Science in 1992 from Syracuse University. He is a senior member of the IEEE.