“System-on-Chip Design and Validation for Emerging IoT Devices”
Thursday, Sept. 6, 1:00 p.m.
Our daily life is intertwined in the fabric of Internet-of-Things (IoT), a fabric in which the number of connected smart computing devices exceeds the human population. Unlike microcontroller-based designs in the past, even resource-constrained IoT devices nowadays incorporate one or more complex System-on-Chips (SoCs). IoT applications bring important considerations such as long application life and dynamic use-case scenarios. Therefore, there is a critical need for IoT devices to dynamically adapt to the environment over the lifetime based on four-way interoperability constraints consisting of reliability, energy, connectivity, and intelligence. It is a major challenge to verify various requirements of SoCs in IoT devices, primarily due to increasing design complexity coupled with shrinking time-to-market constraints. Verification is a major bottleneck in modern chip design life cycle where more than 70% of the resources and engineering time is spent in verification efforts. In the absence of comprehensive SoC verification, vulnerable IoT devices can lead to unintended consequences including damages to critical infrastructure, violating personal privacy, or undermining the credibility of a business.
In this talk, I will present SoC validation challenges and effective solutions across different abstraction layers including both pre- and post-silicon validation and debug. The existing software or hardware verification techniques are suitable for validation of sequential and concurrent (discreet) models, respectively. To verify IoT SoCs, we need to consider sequential (software), discreet (digital) as well as continuous models (analog and mixed signal) of computation and their complex interactions due to the presence of heterogeneous computing paradigms in today’s IoT devices. The core part of my talk will cover a comprehensive SoC design framework consisting of design automation, formal verification, statistical test generation as well as side channel analysis. Finally, I will describe the future IoT design and verification challenges and potential opportunities while considering the trade-off between reliability, energy, connectivity, and intelligence.
Farimah Farahmandi received her Ph.D. from the Department of Computer and Information Science and Engineering at the University of Florida, 2018. She received her B.S. and M.S. from the Department of Electrical and Computer Engineering at the University of Tehran, Iran in 2010 and 2013, respectively. Her research interests include design automation of SoCs and energy-efficient systems, formal verification, post-silicon validation and debug. Her research has resulted in two books, seven book chapters, and fifteen publications in premier ACM/IEEE journals and conferences including IEEE Transactions on Computers, IEEE Transactions on CAD, Design Automation Conference (DAC), and Design Automation and Test in Europe (DATE). Her research has been recognized by several awards including IEEE System Validation and Debug Technology Committee Student Research Award, Gartner Group Info-Tech Scholarship, nomination for Best Paper Award in ASPDAC 2017, and DAC Richard Newton Young Student Fellowship. She was a research intern at Cisco in summer 2016. She has actively collaborated with various research groups (IBM, Intel, NXP, and Cisco) that has led to several joint publications. She currently serves as an Associate Editor of IET Computers & Digital Techniques and as a technical program committee member of International Conference on VLSI Design and International Conference on Embedded Systems. She is a member of IEEE.